This part of IEC 62804 defines procedures to test and evaluate for potential-induced degradation-delamination (PID-d) mode in the laminate of crystalline silicon PV modules— principally those with one or two glass faces. This document evaluates delamination attributable to current transfer between ground and the module cell circuit. Elements driving the delamination that this test is designed to actuate include reduced adhesion associated with damp heat exposure, sodium accumulation at interfaces, and cathodic gas evolution in the cell circuit, metallization, and other components within the PV module activated by the voltage potential. The change in power of crystalline silicon PV modules associated with the stress factors applied (the purview of IEC TS 62804‑1) is not considered in the scope.

Modules are tested in a climactic chamber with damp heat and application of module-rated system voltage to the cell circuit in each polarity that is specified or allowed in the module documentation. This document does not differentiate the effects of some construction methods of mitigating PID—for example, the use of rear rail mounts, edge clips, and insulating frames that may serve to electrically isolate the module faces to varying extents. The actual durability of modules to system voltage stress will depend on the mounting design and the environmental conditions under which the modules are operated. These tests are intended to assess the sensitivity of the PV module laminate to PID-d irrespective of actual stresses under operation in different climates and systems.