What is BS IEC 62531 - Property specification language about?
BS IEC 62531 defines the property specification language (PSL), which formally describes the electronic system behaviour. BS IEC 62531 specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages.
The purpose of BS IEC 62531 is to provide a well-defined language for formal specification of electronic system behaviour, one that is compatible with multiple electronic system design languages, including IEEE Std 1076™ (VHDL®), IEEE Std 1364™ (Verilog®), IEEE Std 1800™ (SystemVerilog®), and IEEE Std 1666™ (SystemC®), to facilitate a common specification and verification flow for multi-language and mixed-language designs.
This standard creates an updated IEEE standard based upon IEEE Std 1850-2005. The updated standard will refine the IEEE standard, addressing errata, minor technical issues, and proposed extensions specifically related to property reuse and improved simulation usability.
Who is BS IEC 62531 - Property specification language for?
BS IEC 62531 on property specification language is useful for:
- Design architects
- Hardware designers
- Verification engineers
- IT experts
Why should you use BS IEC 62531 - Property specification language?
The process of specification has consisted of creating a natural language description of a set of design requirements. This form of specification is both ambiguous and, in many cases, unverifiable due to the lack of a standard machine-executable representation. Furthermore, ensuring that all functional aspects of the specification have been adequately verified (that is, covered) is problematic.
BS IEC 62531 was developed to address these shortcomings. BS IEC 62531 gives the design architect a standard means of specifying design properties using a concise syntax with clearly-defined formal semantics.
Similarly, BS IEC 62531 enables the register transfer level (RTL) implementer to capture design intent in a verifiable form, while enabling the verification engineer to validate that the implementation satisfies its specification through dynamic (that is, simulation) and static (that is, formal) verification means.
Furthermore, BS IEC 62531 provides a means to measure the quality of the verification process through the creation of functional coverage models built on formally specified properties.
In conclusion, BS IEC 62531 provides you with a standard means to create rigorous and machine-executable design specifications.